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1 ? fn9149.2 isl6410, isl6410a single synchronous buck regulators with integrated fet the isl6410, isl6410a are synchronous current-mode pwm regulators designed to provide a total dc-dc solution for microcontrollers, micropro cessors, cplds, fpgas, core processors/bbp/mac, and asics . the isl6410 should be selected for applications using 3.3v 10% as an input voltage and the isl6410a in applications requiring 5.0v 10%. these synchronous current mode pwm regulators have integrated n- and p-channel power mosfets and provide pre-set pin programmable output s. synchronous rectification with internal mosfets is used to achieve higher efficiency and a reduced external component count. the operating frequency of 750khz typical allows the use of small inductor and capacitor values. the device can be synchronized to an external clock signal in the range of 500khz to 1mhz. a power good signal ?pg? is generated when the output voltage falls outside the regulation limits. other features include overcurrent protection and thermal overload shutdown. the isl6410, isl6410a are available in an msop 10 lead package. features ? fully integrated synchronous buck regulator ? pwm fixed output voltage options - 1.8v, 1.5v or 1.2v with isl6410 (vin = 3.3v) - 3.3v, 1.8v or 1.2v with isl6410a (vin = 5.0v) ? continuous output current . . . . . . . . . . . . . . . . . . 600ma ? ultra-compact dc-dc converter design ? stable with small ceramic output capacitors ? high conversion efficiency ? extensive circuit protection and monitoring features - overvoltage, uvlo - overcurrent - thermal shutdown ? available in msop package ? pb-free packaging available applications ? cpus, dsp, cplds, fpgas ? asics ? dvd and dsl applications ?wlan cards ? generic 5v to 3.3v conversion pinout isl6410 (msop) top view ordering information part number temp. range (c) package pkg. dwg. # isl6410iu -40 to 85 10 ld msop m10.118 isl6410iuz (note) -40 to 85 10 ld msop (pb-free) m10.118 isl6410aiu -40 to 85 10 ld msop m10.118 isl6410aiuz (note) -40 to 85 10 ld msop (pb-free) m10.118 note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. pvcc vin gnd pg fb pgnd l en sync vset 1 2 3 4 5 10 9 8 7 6 data sheet june 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 functional block diagram soft start compensation ea gm 750khz oscillator slope compensation en pwm overcurrent, overvoltage logic power good pwm v out uvlo pwm reference 0.45v gate drive current sense zero current detect l pgnd fb pg en sync vin gnd vset pvcc 10f vin 10f 8.2h l1 vout 0.1f notes: 1. vin is 3.3v for isl6410 and 5.0v for isl6410a. 2. vset in the above schematic is connected to vin, so the vout is 1.8v for isl6410 and 3.3v for isl6410a. 2 3 7 6 8 4 5 10 9 1 isl6410, isl6410a
3 isl6410, isl6410a typical application schematics v out vin 3.3v c in c out 10f 10f 8.2h l1 0.1f figure 1. schematic using the isl6410 1.8v 1 2 3 4 5 10 9 8 7 6 isl6410 pvcc vin gnd pg fb pgnd l en sync vset 10% figure 2. schematic using the isl6410a v out vin 5.0v c in c out 10f 10f 12h l1 0.1f 3.3v 1 2 3 4 5 10 9 8 7 6 isl6410a pvcc vin gnd pg fb pgnd l en sync vset 10%
4 absolute maxi mum ratings (note 1) thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v sync, fb, vset & enable input (note 3) . . . . -0.3v to vcc+0.3v esd classification (human body model) . . . . . . . . . . . . . . . .1500v thermal resistance (typical) ja (c/w) msop package (note 4) . . . . . . . . . . . . . . . . . . . . . 128 maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (10s, soldering . . . . . . . . . . . . . 260c ambient temperature range. . . . . . . . . . . . . . . . . . . . -40c to 85c junction temperature range. . . . . . . . . . . . . . . . . . . -40c to 125c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 3. all voltages are with respect to gnd. 4. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications recommended operating conditions unless otherwise noted. v in = 3.3v 10% (isl6410) or 5v 10% (isl6410a), t a = 25c (note 5). parameter test conditions min typ max units v cc supply supply voltage range vin (isl6410) 3.0 3.3 3.6 v vin (isl6410a) 4.5 5.0 5.5 v input uvlo threshold v tr (isl6410) rising 2.62 2.68 2.73 v v tf (isl6410) falling 2.53 2.59 2.64 v v tr (isl6410a) rising 4.27 4.37 4.45 v v tf (isl6410a) falling 4.1 4.22 4.32 v quiescent supply current i out = 0ma - 2.3 - ma shutdown supply current en = gnd, t a = 25c - 5 10 a en = gnd, t a = 85c - 10 15 a thermal shutdown temperature (note 6) rising threshold - 150 - c thermal shutdown hysteresis (note 6) - 20 25 c synchronous buck pwm regulator output voltage isl6410, vsel = l - 1.2 - v isl6410, vsel = h - 1.8 - v isl6410, vsel = open - 1.5 - v isl6410a, vsel = l - 1.2 - v isl6410a, vsel = h - 3.3 - v isl6410a, vsel = open - 1.8 - v output voltage accuracy i out = 3ma, t a = -40c to 85c -1.5 - +1.5 % line regulation i out = 3ma -0.5 - +0.5 % load regulation i out = 3ma to 600ma -1.5 - +1.5 % maximum output current - - 600 ma peak output current limit 700 - 1300 ma pmos r ds(on) i out = 200ma - 230 - m ? nmos r ds(on) i out = 200ma - 230 - m ? efficiency i out = 200ma, v in = 3.3v, v o = 1.8v (isl6410) - 92 - % efficiency i out = 200ma, v in = 5.0v, v o = 3.3v (isl6410a) - 93 - % isl6410, isl6410a
5 pin description vin - supply voltage for the ic. it is recommended to place a 1f decoupling capacitor as close as possible to the ic. gnd - small signal ground for the pwm controller stage. all internal control circuits are referenced to this pin. pg - the power good is an open-drain output. a pull-up resistor should be connected between pg and vin. it is asserted active high when the output voltage reaches 94.5% of the nominal value. fb - the feedback pin is used to sense the output voltage, and should be connected to vout for normal operation. vset - this pin is used to program the output voltages. refer to table 1 below for details. sync - this pin is used for synchronization. the converter switching frequency can be synchronized to an external cmos clock signal in the range of (500khz to 1mhz). en - a logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current to less than 10 a at 25c. this pin should be pulled up to vcc via a 10k resistor. l - this pin is the drain junction of the internal power mosfets and is to be connected to the external inductor. pgnd - power ground. connect all power grounds to this pin. pvcc - this pin provides the input supply for the internal mosfets. it is recommended to place a 1f decoupling capacitor as close as possible to the ic. efficiency i out = 600ma, v in = 5.0v, v o = 3.3v (isl6410a) - 91 - % soft-start time 4096 clock cycles @ 750khz - 5.5 - ms oscillator oscillator frequency 620 750 860 khz frequency synchronization range (f sync ) clock signal on sync pin 500 - 1000 khz sync high level input voltage as % of vin 70 - - % sync low level input voltage as % of vin - - 30 % sync input leakage current sync = gnd or v in -1 - 1 a duty cycle of external clock signal (note 6) 20 - 60 % pgood (isl6410 interfaces to 3.3v logic, isl6410a interfaces to 5.0v logic) rising threshold 1ma minimum source/sink +5.5 8.0 +10.5 % falling threshold -10.5 -8.0 -5.5 % rising/falling hysteresis -1 - % enable en high level input voltage as % of vin 70 - - % en low level input voltage as % of vin - - 30 % en input leakage current en = gnd or v in -1 1 a overvoltage overvoltage threshold 27 30 33 % notes: 5. specifications at -40c and +85c ar e guaranteed by design, not production tested. 6. guaranteed by design, not production tested. electrical specifications recommended operating conditions unless otherwise noted. v in = 3.3v 10% (isl6410) or 5v 10% (isl6410a), t a = 25c (note 5). (continued) parameter test conditions min typ max units table 1. vset isl6410 vo isl6410a vo high 1.8v 3.3v open (nc) 1.5v 1.8v low 1.2v 1.2v isl6410, isl6410a
6 functional description the isl6410, isl6410a is a synchronous buck regulator with integrated n- and p-channel power mosfet and provides pre-set pin programm able outputs. synchronous rectification with internal mosfets is used to achieve higher efficiency and reduced number of external components. operating frequency of 750khz typical allows the use of small inductor and capacitor values. the device can be synchronized to an external clock signal in the range of 500khz to 1mhz. the pg output indicates loss of regulation on pwm output. the pwm is based on the peak current mode control topology with internal slope compensation. at the beginning of each clock cycle, the hi gh side p-channel mosfet is turned on. the current in the inductor ramps up and is sensed via an internal circuit. on exceeding a preset limit the high side switch is turned off causing the pwm comparator to trip. this occurs whenever the output voltage is in regulation or when the inductor current reaches the current limit. after a minimum dead time to prevent shoot through current, the low side n-channel mosfet turns on and the current ramps down. as the clo ck cycle is completed, the low side switch turns off and the next clock cycle is initiated. the control loop is internally compensated thus reducing the amount of external components. the switch current is internally sensed and the maximum current limit is 1300ma peak. synchronization the typical operating frequency for the converter is 750khz. it is possible to synchronize the converter to an external clock frequency in the range of 500khz to 1000khz when an external signal is applied to sync pin. the device will automatically detect and synchr onize to the rising edge of the first clock pulse. if the clock signal is stopped, the converter automatically switches back to the internal clock and continues its operation wit hout interruption. the switch over will be initiated if no rising edge triggers are present on the sync pin for a duration of four clock cycles. soft-start as the en (enable) pin goes high, the soft-start function will generate an internal voltage ramp. this causes the start-up current to slowly rise prev enting output voltage overshoot and high inrush currents. the so ft-start duration is typically 5.5ms with 750khz switching fr equency. when the soft-start is completed, the error amplifie r will be connected directly to the internal voltage reference. enable logic low on en pin forces the pwm section into shutdown. in the shutdown mode all the major blocks of the pwm including power switches, drivers, voltage reference, and oscillator are turned off. undervoltage lockout an undervoltage lockout circuit prevents the converter from turning on when the voltage on vin is less than the values specified in the input uvlo threshold section of the electrical specification. power good this output is asserted high when the pwm is enabled, and vout is within 8.0% typical of its final value, and is active low outside this range. when disabled, the output turns active low. it is recommended to leave the pg pin unconnected when not used. pwm overvoltage and overcurrent protection the pwm output current is sampled at the end of each pwm cycle, exceeding the overcurrent limit, causes a 4 bit up/down counter to increment by one lsb. a normal current state causes the counter to decrement by one lsb (the counter will not however ?rollover? or count below 0000). when the pwm goes into overcurrent, the counter rapidly reaches count 1111 and the pwm output is shut down and the soft-start counter is re set. after 16 clocks the pwm output is enabled and the so ft-start cycle is started. if vout exceeds the overvoltage limit for 32 consecutive clock cycles the pwm output is shut off and the soft-start cycle is initiated. no load operation if there is no load connected to the output, the converter will regulate the output voltage by allowing the inductor current to reverse for a short period of time. output capacitor selection for best performance, a low esr output capacitor is needed. output voltages below 1.8v require a larger output capacitor and esr value to improve the performance and stability of the converter. fo r 1.8v output applications, a ceramic capacitor of 10f or higher value with esr 50m ? is recommended. the rms ripple current is calculated as: l = the inductor value f = the switching frequency i rms co () vo 1 vo vin --------- ? lf ------------------ - 1 23 ---------------- - = isl6410, isl6410a
7 the overall output ripple voltage is the sum of the voltage spike caused by the output capacitor esr and the voltage ripple caused by charge and discharge of the output capacitor: where the highest output voltage ripple occurs at the highest input voltage vin. input capacitor selection the input current to the buck converter is pulsed, and therefore a low esr input capacitor is required. this results in good input voltage filtering and minimizes the interference it causes to other circuits. the input capacitor should have a minimum value of 10 f and a higher value can be selected for improving input voltage filtering. the input capacitor should be rated for the maximum input ripple current calculated as: the worst case rms ripple current occurs at d = 0.5 and is calculated as: irms = io/2. d = duty cycle ceramic capacitors are preferred because of their low esr value. they are also less sensitive to voltage transients when compared to tantalum capacitors. it is good practice to place the input capacitor as close as possible to the input pin of the ic for optimum performance. inductor selection the isl6410 is an internally compensated device and hence a minimum of 8.2 h must be used for the isl6410 and a minimum of 12 h for the isl6410a. the selected inductor must have a low dc resistance and a saturation current greater than the maximum inductor current value can be calculated from the equations below where dil = the peak to peak inductor current l = the inductor value f = the switching frequency ilmax = the max inductor current layout considerations as in all switching power supplie s, the layout is an important step in the design process, more so at high peak currents and switching frequencies. impro per layout practice will give rise to stability and emi issues. it is recommended that wide and short traces are used for the main current paths. the input capacitor should be placed as close as possible to the ic pins. this applies to the output inductor and capacitor as well. the analog ground, gnd, and the power ground, pgnd, need to be separated. use a common ground node to minimize the effects of ground noise. table 2. recommended output capacitors capacitor value esr (m ?) component supplier comments 10 f <50 avx 08056d106kat2a ceramic vo ? vo 1 vo vin --------- ? lf ------------------ - 1 8cof ------------------------- esr + ?? ?? = i rms io max () vo vin --------- 1 vo vin --------- ? ?? ?? = table 3. recommended inductors inductor value dcr (m ?) component supplier 8.2 h75coilcraft mss6122-822mx 12 h 100 coilcraft mss6122-123mx dil vo 1 vo vin --------- ? lf ------------------ - = il max io max dil 2 -------- - + = isl6410, isl6410a
8 performance curves and waveforms figure 3. isl6410 efficiency vs load current figure 4. isl6410 vin vs efficiency figure 5. isl6410a efficiency vs load current figure 6. isl6410a efficiency vs vin figure 7. isl6410 oscillator frequency vs temperature figure 8. isl6410a oscillator frequency vs temperature 1000 100 50 100 80 50 iout load current (ma) efficiency (%) 90 70 60 vout = 1.8v vout = 1.2v vout = 1.5v 3.3 2.9 90 80 70 60 vin input voltage (v) efficiency (%) 3.1 3.5 50 iout = 200ma iout = 600ma 100 1000 100 50 100 80 50 iout load current (ma) efficiency (%) 90 70 60 vout = 3.3v vout = 1.2v vout = 1.8v 5.6 5.0 4.4 vin (v) efficiency (%) 4.8 5.2 4.6 5.4 90 80 70 60 50 100 iout = 600ma iout = 200ma 85 35 -40 800 790 780 770 750 temperature (c) switching frequency (khz) 10 60 -15 760 85 35 -40 780 770 760 750 730 temperature (c) switching frequency (khz) 10 60 -15 740 isl6410, isl6410a
9 ch1 = top, ch2 = middle, ch4 = bottom, where applicable figure 9. switching waveform for isl6410 fi gure 10. switching waveform for isl6410a figure 11. transient load waveform for isl6410 figure 12. transient load waveform for isl6410a figure 13. ripple waveform for isl6410 figure 14. ripple waveform for isl6410a performance curves and waveforms (continued) vout l pin voltage l1 current 0.5s/div ch1 = 0.1v/div, ch2 = 2v/div ch4 = 200ma/div vout l pin voltage l1 current 0.5s/div ch1 = 0.1v/div, ch2 = 2v/div ch4 = 200ma/div vin = 5.0v, vout = 1.2v, iout = 0.5a 0.5ms/div ch1 = 0.2v/div, ch4 = 200ma/div vout iout vin = 3.3v, vout = 1.2v ch1 = 0.1v/div, ch4 = 200ma/div vout iout vin = 5.0v, vout = 1.2v 0.5ms/div ch1 = 20mv/div vin = 3.3v, vout = 1.2v 1s/div vout 1s/div ch1 = 20mv/div vin = 5.0v, vout = 1.2v vout isl6410, isl6410a
10 figure 15. switching harmonics and noise for isl6410 figure 16. switching harmonics and noise for isl6410a performance curves and waveforms (continued) noise level 761khz = -54.0dbm -120 -40 -110 -50 -60 -70 -80 -90 -100 vin = 3.3v, vout = 1.2v center 2.75mhz, span = 4.5mhz noise level 732khz = -65.3dbm center 2.75mhz, span = 4.5mhz -120 -40 -110 -50 -60 -70 -80 -90 -100 vin = 5.0v, vout = 1.2v isl6410, isl6410a
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com isl6410, isl6410a mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m10.118 (jedec mo-187ba) 10 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.020 bsc 0.50 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n10 107 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 5 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 0 12/02

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